This layer contains recipes for Hardware Description Languages (HDL) tools, which includes tools for simulation, synthesis, etc.

Setup information

Git repository

https://github.com/nathanrossi/meta-hdl web repo

Last commit: 1 week, 1 day ago (master branch)

Maintainer

Dependencies

The meta-hdl layer depends upon:

Recipe name Version Description
arachne-pnr 0+gitX Arachne Place and Route tool for iCE40 FPGAs
berkeley-abc 1.01+gitX Berkeley ABC: System for Sequential Logic Synthesis and Formal Verification
fpga-toolkit 1.0 Portable toolkit/SDK for FPGA tools
icarus-verilog 10.2+gitX Icarus Verilog is a Verilog simulaton and synthesis tool
icestorm 0+gitX Project IceStorm aims at reverse engineering, documenting and tools for Lattice iCE40 FPGAs
libtrellis 0+gitX Documenting the Lattice ECP5 bit-stream format.
migen 0.8+gitX A Python toolbox for building complex digital hardware
netlistsvg 0.0.1 draws an SVG schematic from a JSON netlist
nextpnr-ecp5 0+gitX nextpnr, a portable FPGA place and route tool
nextpnr-ice40 0+gitX nextpnr, a portable FPGA place and route tool
picosoc-hx8k 1.0 PicoSoC - A simple example SoC using PicoRV32
prjtrellis-db 0+gitX Project Trellis database
prjxray 0+gitX Documenting the Xilinx 7-series bit-stream format.
prjxray-db 0+gitX Project X-Ray database
python3-colorama 0.3.9 Cross-platform colored terminal text.
python3-yapf 0.24.0 A formatter for Python files
symbiflow-arch-defs 0+gitX FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
symbiflow-arch-defs-tests 0+gitX FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
verilog-to-routing 1.0 The Verilog to Routing (VTR) project provides open-source CAD tools for FPGA architecture and CAD research.
yosys 0.8+gitX Yosys, a framework for Verilog RTL synthesis
lm32 LaticeMico32 Generic Machine
picosoc picosoc with picorv32 RISC-V processor
Date/time Errors Warnings
Nov. 14, 2018, 8:47 a.m.
Nov. 6, 2018, 11:27 a.m.
Nov. 1, 2018, 12:23 p.m.