meta-intelfpga
With this layer the board support package (BSP) for ARM based Intel (ALTERA) SoC-FPGAs (SoCFPGA) is added to the Yocto Project. It can bring with the rstools useful tools to interact with the FPGA fabric (e.g. Changing the FPGA configuration or accessing all ARM AXI Bride interfaces). In addition, is the ARM Development Studio (DS-5) Streamline Server gator included. Usually the Yocto Project can generate all required components (rootfs, device tree, bootloaders,...) to boot up a final embedded Linux. But this is not compatible with Intel's Boot flow. This Bootflow uses the Intel Embedded Design Suite (SoC EDS) to build the Linux Device Tree and all necessary bootloaders. For that reason, I designed a version that is compatible with Intel's development tools. This includes the board specific u-boot- and device tree-generation and the support for only the .tar.gz-file type for the rootfs. I used this layer to build rsyocto, an open source embedded Linux Distribution for Intel SoC-FPGAs, by myself. The flexibility of my own rsyocto build system allows you to use it for your own projects with your custom embedded Linux. I designed a Python script that can automate the boot image desgin with a specifiable partition table. It can generate a bootable image file with Kernel-,bootloader- and user-files. With the flexibility of this script it is compatible with Intel SoC-EDS build flow for example it can pre-install FPGA configuration files. You can find step-by-step instructions for using this BSP layer on Github.
Git repository
https://github.com/robseb/meta-intelfpga web repo
Last commit: 5 months, 2 weeks ago (master branch)
Maintainer
- Robin Sebastian email
Recipe name | Version | Description |
---|---|---|
dumpbridge | cyclone5 | Write all Intel SoC-FPGA AXI Bridges (lw2fpga; hps2fpga bridge) |
gator | gitX | ARM Development Studio (DS-5) Streamline Gator daemon |
gator | gitX | ARM Development Studio (DS-5) Streamline Gator daemon |
gator | gitX | ARM Development Studio (DS-5) Streamline Gator daemon |
initscript | 0.10.0 | |
linux-altera | 6.7 | Linux kernel |
linux-altera | 6.6 | Linux kernel |
linux-altera | 6.5 | Linux kernel |
linux-altera | 6.2 | Linux kernel |
linux-altera | 6.1 | Linux kernel |
linux-altera | 6.0 | Linux kernel |
linux-altera | 5.8 | Linux kernel |
linux-altera-lts | 6.1.68-lts | Linux kernel |
linux-altera-lts | 6.1.55-lts | Linux kernel |
linux-altera-lts | 6.1.38-lts | Linux kernel |
linux-altera-lts | 6.1.20-lts | Linux kernel |
linux-altera-lts | 5.4.54-lts | Linux kernel |
linux-altera-lts | 5.15.90-lts | Linux kernel |
linux-altera-lts | 5.15.80-lts | Linux kernel |
linux-altera-lts | 5.15.70-lts | Linux kernel |
linux-altera-lts | 5.10.60-lts | Linux kernel |
linux-altera-lts | 5.10.100-lts | Linux kernel |
mselfpga | cyclone5 | Read Intel SOC-FPGA MSEL (mode select) tool |
mselfpga | arria10 | Read Intel SOC-FPGA MSEL (mode select) tool |
readbridgesfpga | cyclone5 | Read all Intel SoC-FPGA AXI Bridges (lw2fpga; hps2fpga bridge) |
readbridgesfpga | arria10 | Read all Intel SoC-FPGA AXI Bridges (lw2fpga; hps2fpga bridge) |
readfgpipg | arria10 | Read GPI (general purpose input) register of the Intel FPGA Manager |
readfgpipga | cyclone5 | Read GPI (general purpose input) register of the Intel FPGA Manager |
resetfabricfpga | cyclone5 | Reset the FPGA Fabric |
resetfabricfpga | arria10 | Reset the FPGA Fabric |
resetfpga | cyclone5 | Reset the FPGA Fabric |
statusfpga | cyclone5 | Read the FPGA Fabric Status |
statusfpga | arria10 | Read the FPGA Fabric Status |
writebridgefpga | cyclone5 | Write all Intel SoC-FPGA AXI Bridges (lw2fpga; hps2fpga bridge) |
writebridgefpga | arria10 | Write all Intel SoC-FPGA AXI Bridges (lw2fpga; hps2fpga bridge) |
writeconfigfpga | cyclone5 | Tool to load a new FPGA Configuration for Intel SoC-FPGAs |
writeconfigfpga | arria10 | Tool to load a new FPGA Configuration for Intel SoC-FPGAs |
writegpofpga | cyclone5 | Write to the GPO (general purpose output) register of the Intel FPGA Manager |
writegpofpga | arria10 | Write to the GPO (general purpose output) register of the Intel FPGA Manager |