This is the general hardware specific BSP overlay for the RISC-V based devices. More information can be found at: (Official Site)

Setup information

Git repository web repo

Last commit: 3 days, 1 hour ago (master branch)



The meta-riscv layer depends upon:

Recipe name Version Description
gdb riscv GNU debugger
gdb-cross-canadian-i586 riscv GNU debugger (cross-canadian gdb for i586 target)
gdb-cross-i586 riscv GNU debugger
libffi 3.3-rc0 A portable foreign function interface library
linux-riscv 4.20-rc5+gitX Linux kernel
linux-riscv 4.19+gitX Linux kernel
linux-riscv 4.18+gitX RISC-V Community BSP RISC-V Linux kernel with backported features and fiexes
riscv-fesvr 1.0 RISC-V Front-end Server
riscv-initramfs-image 1.0 initramfs image to be used together with SiFive Unleashed board as the board currently only supports booting from a ramdisk image
riscv-pk 1.0 RISC-V Proxy Kernel
riscv-spike 1.0 RISC-V Spike ISA Simulator
baremetal-riscv32 a generic riscv32
baremetal-riscv64 a generic riscv64
freedom-u540 HiFive Unleashed development board
qemuriscv32 a generic riscv32
qemuriscv64 a generic riscv64
Date/time Errors Warnings
Dec. 13, 2018, 6:26 p.m.
Dec. 13, 2018, 3:11 a.m.
Dec. 11, 2018, 2:17 a.m.
Dec. 10, 2018, 8:11 p.m.
Dec. 8, 2018, 1:02 a.m.
Dec. 3, 2018, 10:41 p.m.
Nov. 30, 2018, 6:17 p.m.
Nov. 30, 2018, 2:59 a.m.
Nov. 29, 2018, 11:54 p.m.