This layer contains recipes for Hardware Description Languages (HDL) tools, which includes tools for simulation, synthesis, etc.

Setup information

Git repository

https://github.com/nathanrossi/meta-hdl web repo

Last commit: 3 months, 3 weeks ago (master branch)

Maintainer

Dependencies

The meta-hdl layer depends upon:

Recipe name Version Description
arachne-pnr 0+gitX Arachne Place and Route tool for iCE40 FPGAs
berkeley-abc 1.01+gitX Berkeley ABC: System for Sequential Logic Synthesis and Formal Verification
boolector 3.1.0+gitX Boolector is a Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions.
btor2tools 1.0.0+gitX Btor2tools is a generic parser and tool package for the BTOR2 format.
cryptominisat 5.11.15+gitX CryptoMiniSat is an advanced incremental SAT solver.
foboot 0+gitX Bootloader for Fomu
fomu-workshop-litex-rgb 0.1+gitX Fomu Workshop litex rgb
fomu-workshop-riscv-blink 0.1+gitX Fomu Workshop riscv-blink
fomu-workshop-verilog-blink 0.1+gitX Fomu Workshop verilog blink
fpga-toolkit 1.0 Portable toolkit/SDK for FPGA tools
hdl-build-all 1.0 Build all the meta-hdl recipes for target, native and nativesdk
icarus-verilog 12.0+gitX Icarus Verilog is a Verilog simulaton and synthesis tool
icestorm 0+gitX Project IceStorm aims at reverse engineering, documenting and tools for Lattice iCE40 FPGAs
linux-on-litex-vexriscv 0+gitX Experiments with Linux on LiteX-VexRiscv
linux-versa-ecp5-vexriscv 5.17+X Mainline Linux kernel
litedram 2023.08+master+gitX Small footprint and configurable DRAM core
litedram 2023.08+gitX Small footprint and configurable DRAM core
liteeth 2023.08+master+gitX Small footprint and configurable Ethernet core
liteeth 2023.08+gitX Small footprint and configurable Ethernet core
litehyperbus 2022.04+master+gitX Small footprint and configurable HyperBus core
litehyperbus 2022.04+gitX Small footprint and configurable HyperBus core
liteiclink 2023.08+master+gitX Small footprint and configurable Inter-Chip communication cores
liteiclink 2023.08+gitX Small footprint and configurable Inter-Chip communication cores
litepcie 2023.08+master+gitX Small footprint and configurable PCIe core
litepcie 2023.08+gitX Small footprint and configurable PCIe core
litesata 2023.08+master+gitX Small footprint and configurable SATA core
litesata 2023.08+gitX Small footprint and configurable SATA core
litescope 2023.08+master+gitX Small footprint and configurable embedded FPGA logic analyzer
litescope 2023.08+gitX Small footprint and configurable embedded FPGA logic analyzer
litesdcard 2023.08+master+gitX Small footprint and configurable SDCard core
litesdcard 2023.08+gitX Small footprint and configurable SDCard core
litespi 2023.08+master+gitX Small footprint and configurable SPI core
litespi 2023.08+gitX Small footprint and configurable SPI core
litevideo 2021.08+gitX Small footprint and configurable video cores
litex 2023.08+master+gitX LiteX is a FPGA design/SoC builder that can be used to build cores, create SoCs and full FPGA designs.
litex 2023.08+gitX LiteX is a FPGA design/SoC builder that can be used to build cores, create SoCs and full FPGA designs.
litex-boards 2023.08+master+gitX LiteX boards files
litex-boards 2023.08+gitX LiteX boards files
litex-pythondata-cpu-vexriscv 2023.08+master+gitX LiteX - VexRiscV CPU
litex-pythondata-cpu-vexriscv 2023.08+gitX LiteX - VexRiscV CPU
litex-pythondata-cpu-vexriscv-smp 2023.08+master+gitX LiteX - VexRiscV CPU SMP
litex-pythondata-cpu-vexriscv-smp 2023.08+gitX LiteX - VexRiscV CPU SMP
litex-pythondata-misc-tapcfg 2023.08+gitX LiteX - tapcfg
litex-pythondata-software-compiler-rt 2023.08+gitX LiteX - compiler_rt software
litex-pythondata-software-picolibc 2023.08+gitX LiteX - picolibc
micropython 1.10+fomu+X MicroPython - a lean and efficient Python implementation for microcontrollers and constrained systems.
migen 0.9.2+gitX A Python toolbox for building complex digital hardware
netlistsvg 0.0.1 draws an SVG schematic from a JSON netlist
nextpnr-bbasm 0.6+gitX nextpnr, a portable FPGA place and route tool
nextpnr-ecp5 0.6+gitX nextpnr, a portable FPGA place and route tool
nextpnr-ecp5-chipdb 0.6+gitX nextpnr, a portable FPGA place and route tool
nextpnr-ice40 0.6+gitX nextpnr, a portable FPGA place and route tool
nextpnr-ice40-chipdb 0.6+gitX nextpnr, a portable FPGA place and route tool
nextpnr-xilinx 0+gitX nextpnr, a portable FPGA place and route tool
nextpnr-xilinx-chipdb 0+gitX nextpnr, a portable FPGA place and route tool
nextpnr-xilinx-examples-arty-a35 0+gitX nextpnr, a portable FPGA place and route tool
opensbi 0.8+litex+gitX RISC-V Open Source Supervisor Binary Interface (OpenSBI)
packagegroup-fpga-tools 1.0 Packages for FPGA tools and synthesis flows
picosoc-hx8k 1.0 PicoSoC - A simple example SoC using PicoRV32
picosoc-icebreaker 1.0 PicoSoC - A simple example SoC using PicoRV32
prjtrellis 0+gitX Documenting the Lattice ECP5 bit-stream format.
prjtrellis-db 0+gitX Project Trellis database
prjtrellis-examples-versa5g 0+gitX Documenting the Lattice ECP5 bit-stream format.
prjxray 0+gitX Documenting the Xilinx 7-series bit-stream format.
prjxray-db 0+gitX Project X-Ray database
python3-fasm 1.0 FPGA Assembly (FASM) Parser and Generator
python3-intervaltree 3.0.2 Editable interval tree data structure for Python 2 and 3
python3-jsonmerge 1.5.2 Merge a series of JSON documents
python3-pyjson5 1.6.2 JSON5 serializer and parser for Python 3 written in Cython.
python3-textx 2.3.0 Domain-Specific Languages and parsers in Python made easy
python3-xc-fasm 1.0 Library to convert FASM files to bistream
python3-yapf 0.24.0 A formatter for Python files
sby 0+gitX SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
symbiflow-arch-defs 0+gitX FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
symbiflow-arch-defs-tests 0+gitX FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
tinyfpga-programmer 1.0 An open source USB bootloader for FPGAs
verilator 5.016+gitX Verilator open-source SystemVerilog simulator and lint system
verilog-to-routing 1.0 The Verilog to Routing (VTR) project provides open-source CAD tools for FPGA architecture and CAD research.
xc3sprog 0.0+svnrX xc3sprog is a suite of utilities for programming Xilinx FPGAs, CPLDs, and EEPROMs
yices2 2.6.4+gitX Yices 2 is a solver for Satisfiability Modulo Theories (SMT) problems.
yosys 0.34+gitX Yosys, a framework for Verilog RTL synthesis
z3 4.12.2+gitX Z3 is a theorem prover from Microsoft Research.
fomu fomu with 32-bit RISC-V litex SoC
lm32 LaticeMico32 Generic Machine
picosoc picosoc with picorv32 RISC-V processor
versa-ecp5 Lattice Versa ECP5 Evaluation Board